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| L6611 DIGITALLY PROGRAMMABLE SECONDARY HOUSEKEEPING CONTROLLER s s s s s s s s s s OV/UV DETECTION FOR 3.3V, +5V, 12V RAILS AND 5V (OR 3.3V) AUX. VOLTAGE AC MAINS UV (BROWNOUT) DETECTION WITH HYSTERESIS ON-LINE DIGITAL TRIMMING FOR 5V/12V, 3.3V, 5V (OR 3.3V) AUX. FEEDBACK REFERENCES AND AC MAINS UV. DIGITALLY SELECTABLE OPTIONS ERROR AMPLIFIERS FOR 5V/12V RAILS (MAIN SUPPLY), 3V3 POST-REGULATOR (MAG_AMP OR LINEAR) AND AUXILIARY SUPPLY. MAIN SUPPLY ON/OFF CONTROL AND POWER GOOD SIGNAL 50mA CROWBAR DRIVE FOR AUXILIARY OUTPUT OVP. OPEN GROUND PROTECTION 8ms DIGITAL SOFT START 64 ms UV/OC BLANKING AT START-UP BCD TECHNOLOGY DIP20 SO20 ORDERING NUMBERS: L6611N L6611D L6611DTR(T & Reel) APPLICATIONS s SWITCHING POWER SUPPLIES FOR DESKTOP PC'S, SERVERS AND WEB SERVERS s SUPERVISOR FOR DISTRIBUTED POWER TYPICAL APPLICATION CIRCUIT +12V + WIDE RANGE MAINS +5V COM -12V MAIN CONTROL +3.3V +5Vaux AUXILIARY CONTROL Bout VDD Cout Dmon 12V 5V -12V 3V3 MFault Aout Gnd L6611 April 2002 1/28 L6611 BLOCK DIAGRAM Binv 2.50V(B) +3V3 +3V3 3V3 +5V UV uv ov +5V 2.50V(A) uv +5V Bout 1.25V (B) Logic and Programmable Trimming Aout Soft Start ov +12V UV uv ov OV ov uv -12V +12V +/-12V UV +5V +12V Ainv Gnd 2.50V( A) U V ACsns Vdd Vdd Reset _ + L 2.50V( C) 50uA V r e f Disable 1.25V(B) 2.50V(B) 2.50V( C) 1.25V( A) Mfault 1.25V (A) Cout 10mA OCP Bounce Cinv PW -OK / Data Vdd PS -ON / Clock - Prog Vdd 2.50V(B) 2.50V( B) ov Dmon uv ov Debounce 75ms Programming input Vreg Vdd Dfault 2/28 L6611 DESCRIPTION The L6611 is a control and housekeeping IC developed in BCD technology; it is intended for acting at the secondary side of desktop PC's or server's switching power supplies, in presence of standard voltage rails (+3.3V, +5V, 12V) generated by a main converter and of a supply line generated by an auxiliary converter. The typical application circuit is showed on the front page. The Housekeeping's main function is to control and monitor the voltages generated by both the main and the auxiliary converter: it senses those voltages, sends feedback signals to the primary controllers for regulation and, upon detection of an undervoltage (UV), or overvoltage (OV) condition, reports such fault and takes proper action to protect the system. However, the peculiar feature of this IC is its digital programming capability that enables an accurate trimming of the output voltage rails during production test via software, without any use of external discrete trimming components or need for manual intervention on the PSU. It is also possible to program some of the monitoring functions and select how UV and OC conditions are handled in the main converter: whether latched-mode (the information is latched and released only by forcing the restart of the IC) or bouncing-mode (an attempt is made to automatically restart the converter after 1 second wait). A key feature of this IC is its contribution to a very low external component count. Besides the extensive use of onboard programmable switches, which prevents the need for external trimming components, the IC embeds reference voltages, error amplifiers and most of the housekeeping circuitry normally required. PIN CONNECTION (top view) MFAULT Binv Bout Aout Ainv Cout Cinv Dmon DFAULT Vdd 12V 5V 3V3 PROG GND -12V VREF PS-ON PW-OK ACsns PIN DESCRIPTION Pin # Name Description 1 Main converter on/off control. This pin is a 10mA current sink used for driving an opto-isolator. It is normally low when PS-ON (#13) is pulled low. If a fault is detected or PS-ON goes high, this MFAULT pin goes high too. To allow power up, the functions are digitally blanked out for a period (UVB function) and MFAULT (#1) stays low. There is no delay for the OV protection function. Binv Inverting input to the error amplifier for the 3V3 post-regulator (either mag-amp or linear). The non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed. Output of the 3V3 error amplifier. It typically drives either a PNP transistor that sets the mag-amp core or the pass element of a linear regulator. Also node for error amplifier compensation. The maximum positive level of this output is clamped at about 3.5V to improve response time. Large signal slew rate is limited to reduce noise sensitivity. 2 3 Bout 3/28 L6611 PIN DESCRIPTION (continued) Pin # 4 Name Aout Description Output of the error amplifier for the main converter. This pin typically drives an optocoupler and is also used for compensation along with Ainv (pin #5). Main loop error amplifier inverting input. The non-inverting input is connected to an internal 2.5V reference that can be digitally trimmed. A high impedance internal divider from +12V and +5V UV/OV sense pins (#19, #20) eliminates the need for external divider in most applications. The pin is used for error amplifier compensation. Auxiliary loop optocoupler drive. Also node for error amp compensation. Large signal slew rate is limited to reduce sensitivity to switching noise. Inverting input for Auxiliary error amplifier. The non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed. Dual or Auxiliary UV/OV monitor, Dmon is programmable to monitor 3V3 or 5V. To allow a correct power up, the UV function on this pin is blanked out during initial start-up. There is no delay for the OV function. Dual or Auxiliary fault protection. When Dmon (#8) recognizes an over voltage, DFAULT and MFAULT (#1) go high. DFAULT is capable of sourcing up to 50mA. Possible applications are a crowbar across the Auxiliary output or an opto-coupled fault signal to the primary side. Positive input supply voltage. Vdd is normally supplied from the Auxiliary power supply output voltage. If Vdd-UVL detects a sustained under voltage, PW-OK (#12) will be pulled low and sending MFAULT (#1) high will disable the main converter. Analog of bulk voltage for AC fail warning. The usual source of this analog pin is one of the secondary windings of the main transformer. Hysteresis is provided through a trimmable 50A current sink on this pin that is activated as the voltage at the pin falls below the internal reference (2.5V). Power good signal for the Main converter. When asserted high, this pin indicates that the voltages monitored are above their UV limits. There will be typically 250ms delay from the Main outputs becoming good and PW-OK being asserted. This is nominally an open drain signal. To improve robustness, this output has a limited current sink capability. In programming mode, this pin is used for data input; then the absolute maximum rating will be Vdd+0.5V. Control pin to enable the Main converter. This pin has debouncing logic. A recognized high value on this pin will cause PW-OK (#12) to go immediately low and, after a delay of 2.5ms, to shut down the main PWM by allowing MFAULT (#1) to go high. During normal operation (or if not used) this pin has to be connected to a voltage lower than 0.8V. In programming mode, this pin will be used to clock serial data into the chip. 2.5V reference for external applications. This is a buffered pin. Shorting this pin to ground or to Vdd (#10) will not affect integrity of control or monitor references. An external capacitor (max. 100nF) is required whenever the pin is loaded (up to 5 mA), otherwise it can be left floating. -12V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #14), the function will be disabled. Ground pin. The connection integrity of this pin is constantly monitored and in case of either a bond wire or a PCB trace going open, MFAULT (#1) and DFAULT (#9) will be forced high switching off the supply. The chip has 2 operating modes, depending on PROG input pin biasing: - normal mode: PROG should be floating or shorted to ground; - programming mode: forcing PROG high (+5V), the chip enters programming mode. PW_OK (#12) and PS_ON (#13) pins are disconnected from their normal functionality and they become inputs for DATA and CLOCK allowing the chip to be programmed. The programming mode allows selecting some options and adjusting some setpoints; 5 Ainv 6 7 Cout Cinv 8 Dmon 9 DFAULT 10 Vdd 11 ACsns 12 PW-OK /Data 13 PS-ON / Clock 14 VREF 15 -12V 16 GND 17 PROG 4/28 L6611 PIN DESCRIPTION (continued) Pin # 18 19 Name 3V3 5V Description 3V3 UV/OV monitor. It uses a separate reference to the feedback reference. Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference separate from that used for feedback. This pin connects the 5V part of the Main error amplifier feedback divider. Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a reference separate from that used for feedback. This pin connects the 12V part of the Main error amplifier feedback divider. 20 12V FUNCTION DESCRIPTION Name OVP Description Whenever one of the Main output voltages is detected going above its own OVP threshold, this function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON (#13) switch or by reducing Vdd (#10) below the UV threshold. Whenever one of the Main output voltages is detected going under its own UVP threshold, this function sets MFAULT (#1) high; if latch mode has been selected, this function will be latched. Otherwise an attempt will be made to restart the device after 1 second delay. If ACsns (#11) is low due to a brownout condition, UVP is disabled. Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the auxiliary converter the timing starts as the IC has a valid supply, for the main converter it starts as the ACsns pin detects a valid input voltage for the converter. PW-OK delay. After power-up, when the all of the monitored voltages are above their own UV threshold the PW-OK pin (#12) will be kept low for additional 250ms (typ.) to make sure all the outputs are settled. Power-off delay. As soon as PS-ON (#13) pin is recognized high, indicating an imminent turn-off condition, PW-OK (#12) pin will go low immediately . The converter will be turned off after a delay of 2.5ms. The PS-ON signal input has debounce logic to prevent improper activation. All of the monitored inputs have digital filtering/debounce logic on board for high noise immunity. AC sense hysteresis. Programmable hysteresis is provided on the ACsns input (#11) to avoid undesired shutdown caused by noise as the voltage at the pin is near the threshold or by the voltage ripple across the bulk capacitor. Vdd is monitored for overvoltage. If an overvoltage is detected, MFAULT (#1) and DFAULT (#9) are latched high. To prevent false signals of any of IC's output pins, an under voltage lock-out circuit monitors Vdd and keeps all IC's output at their default OFF level until Vdd reaches a sufficient minimum voltage for ensuring integrity. When Vdd goes below the UV threshold, all latches are reset and volatile programming memory cleared. Dmon (#8) is monitored to detect an overvoltage condition; in this case MFAULT (#1) and DFAULT (#9) are latched high. Dmon (#8) is monitored to detect an undervoltage condition; in this case MFAULT (#1) is latched high and Cout (#6) is pulled low. UVP UVB PW-OK delay OFF delay Debounce AC-hysteresis Vdd-OVP Vdd-UVL Dual-OVP Dual-UVP 5/28 L6611 FUNCTION DESCRIPTION (continued) Name Description The IC provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0V to 2.5V for the A error amplifier reference voltage, in order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up. In fact, if this reference gets the nominal value as soon as the power-up occurs, the A E/A will go out of regulation and tend to sink much more current, thus forcing PWM to work with the maximum duty-cycle. This option allows setting either latched-mode or auto restart after 1 second delay in case of undervoltage faults. Soft-start Bounce or Latch-mode ABSOLUTE MAXIMUM RATINGS Symbol Vdd Supply voltage Voltage on PROG, PS-ON/Clock, DFAULT, VREF, and error amplifier pins Voltage on MFAULT, PW-OK, Dmon and positive UV, OV, OC, AC sense pins. Voltage on and -12V UV/OV sense pin Maximum current in ESD clamp diodes TJ TSTO TL Operating Junction Temperature Storage Temperature Lead Temperature (soldering, 10 seconds) Parameter Value -0.5 to +7 -0.5 to Vdd+0.5 -0.5 to +16 -16 to +5 10 -25 to 150 -50 to 150 300 Unit V V V V mA C C C THERMAL DATA Symbol Rth j-amb Parameter Max. Thermal Resistance junction-to-ambient (*) DIP20 70 SO20 120 Unit C/W (*) mounted on board 6/28 L6611 ELECTRICAL CHARACTERISTCS (unless otherwise specified: TJ = 0 to 105C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol SUPPLY SECTION VDD(ON) Start-up threshold 4.2 3.7 0.25 6.1 No Fault 4.3 3.8 0.5 6.3 5 4.6 4.1 0.75 6.8 7 V V V V mA Parameter Test Condition Min. Typ. Max. Unit VDD(OFF) Minimum operating voltage after turn-on VDD(H) VDDOV IDD-ON Hysteresis Vdd overvoltage Operating supply current FAULT THRESHOLDS Vout = 3.3V UV OV 3V3 undervoltage 3V3 overvoltage 3V3 bias current Vout = 12V UV OV 12V undervoltage 12V overvoltage 12V bias current Vout = -12V UV OV VD -12V undervoltage -12V overvoltage -12V disable voltage -12V bias current Vout = 3.3V Aux/Dual (Dmon option) UV OV 3V3 undervoltage 3V3 overvoltage 2.80 4.00 2.90 4.15 3.00 4.30 V V Voltage to disable comparator -9.00 -14.4 1.3 -65 -9.50 -15.0 1.5 -50 -10.0 -15.6 1.7 V V V A 10.60 13.50 10.80 14.00 100 11.00 14.50 130 V V A 2.80 4.00 2.90 4.15 50 3.00 4.30 65 V V A Vout = 5V Aux/Dual (Dmon option) UV OV 5V undervoltage 5V overvoltage Bias current ACsense / Hysteresis Bias current VACsns = 2.7V 5 10 A 4.25 6.00 4.40 6.25 50 4.55 6.50 65 V V A 7/28 L6611 ELECTRICAL CHARACTERISTCS (continued) (unless otherwise specified: TJ = 0 to 105C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol UV Parameter AC undervoltage Trim range Trim resolution IACH Hysteresis current Hysteresis trim range HS Hysteresis adjust step 20 -20 5 Test Condition Min. 2.375 -5 0.64 50 80 +20 Typ. 2.50 Max. 2.625 +5 Unit V % % A % % FAULT OUTPUTS VPOKH VPOKL IL MFISNK PW-OK high state PW-OK low state MFAULT high state leakage MFAULT sink current MFAULT OV debounce MFAULT debounce 12V UV MFAULT debounce +5V, 3V3, UV DFIOH DFVOH DFAULT output high source current DFAULT output high voltage No faults ISINK = 15mA PS-ON = high PS-ON = low, VMFAULT = 4V Minimum OV pulse before MFAULT is latched. Minimum UV pulse before MFAULT is latched. Minimum UV pulse before MFAULT is latched. Overvoltage condition VDFAULT = 1.5V IDFAULT = 0mA, Tamb = 25oC, Overvoltage condition IDFAULT = 1mA, no faults Minimum OV pulse before DFAULT is latched. Minimum UV pulse before DFAULT is latched. 6 4 4 250 -25 10 6 6 450 -50 3 0.4 1 15 8 8 650 -95 V V A mA s s s mA 2.1 2.4 2.7 V VOUT DFAULT output low voltage DFAULT OV debounce DFAULT UV debounce 0.3 4 250 0.5 6 450 0.7 8 650 V s s START-UP / SHUTDOWN FUNCTIONS t5 DFAULT UV blanking delay Delay from VDD(on) to DFAULT UV active. Delay from ACSNS high to Main UV active Main's UV good to PW-OK high Delay from PS-ON input to MFAULT 44 64 84 ms t1 MFAULT UV blanking delay 44 64 84 ms t2 t4 (tDELAY) PW-OK blanking delay PS-ON delay time 175 1.75 250 2.5 325 3.25 ms ms 8/28 L6611 ELECTRICAL CHARACTERISTCS (continued) (unless otherwise specified: TJ = 0 to 105C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol VIH VIL Parameter PS-ON Input High Voltage PS-ON Input Low Voltage PS-ON Input high clamp RPS-ON t3 tSS VSTEP PS-ON Pull-up to VDD PS-ON debounce Error Amp. A Soft-Start period Soft Start Step IPS-ON = 100 A VPS-ON = 0V PS-ON input minimum pulse width for a valid logic change. VFB quasi-monothonic ramp from 0 to 2.5V Ramp 0V to 2.5V 25 50 Vdd +0.7 50 75 8 39 100 100 Test Condition IIN = -200A Min. 2.0 0.8 Typ. Max. Unit V V V K ms ms mV VOLTAGE REFERENCE (BUFFERED EXTERNAL PIN) VREF ISC Output Voltage Short circuit current IREF = 1 - 5 mA; CREF = 47nF VREF = 0 2.375 2.50 10 2.625 20 V mA MAIN CONVERTER FEEDBACK (ERROR AMPLIFIER A) VFB Input Voltage Trim Range Trim resolution ZFB Divider impedance Temperature coefficient W5 AVOL GBW PSRR IOUTL IOUTH VOUTH VOUTL Divider 5/12 weighting Voltage gain Unity gain bandwidth Power supply rejection ratio Output sink current Output source current Output high level Output low level 4.5V 9/28 L6611 ELECTRICAL CHARACTERISTCS (continued) (unless otherwise specified: TJ = 0 to 105C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol Parameter Trim resolution IBIAS AVOL GBW PSRR IOUTL IOUTH VOUTH VOUTL Input bias current Voltage gain Unity gain bandwidth Power supply rejection ratio Output sink current Output source current Output high level Output low level 4.5V VCLOCKLO Clock Input Low VCLOCKHI Clock Input High 10/28 L6611 ELECTRICAL CHARACTERISTCS (continued) (unless otherwise specified: TJ = 0 to 105C; V DD = 5V, V3V3 = 3.3V, V5V = 5V, V -12V = -12V, , VDmon = VDD, PS-ON = low) Symbol FCLOCK VDATALO VDATAHI IFUSE tFUSE Parameter Clock Frequency Data Input Low Data Input High PROM Fuse Current PROM Fusing Time 2 400 3 Test Condition Min. Typ. Max. 0.8 1.5 Unit MHz V V mA ms 11/28 L6611 TYPICAL ELECTRICAL CHARACTERISTICS Figure 1. Supply start-up, UV and OV 6.5 Figure 4. Monitored inputs bias current 80 VDD [V] IB [A] over voltage 5.5 70 5Voutput 60 12Voutput 4.5 start-up UV 50 3.3Voutput 40 3.5 -50 -25 0 25 50 T [OC] 30 75 100 125 150 -50 -25 0 25 50 75 100 125 150 T [OC] Figure 2. IC Supply current vs. supply voltage IDD [mA] 10 8 Figure 5. 3.3V fault thresholds 5 V3.3V [V] Dmon = VDD Tj = 25 C 4 overvoltage 6 4 3 2 0 2 undervoltage 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 150 VDD [V] T [OC] Figure 3. IC Supply current 7 IDD [mA] Figure 6. 5V fault thresholds 7 V5V [V] 6 6 overvoltage 5 5 4 4 undervoltage 3 -50 -25 0 25 50 75 100 125 150 T [ OC] 3 -50 -25 0 25 50 T [OC] 75 100 125 150 12/28 L6611 TYPICAL ELECTRICAL CHARACTERISTICS (continued) Figure 7. 12V fault thresholds 15 Figure 10. -12V fault thresholds -6 V+12V [V] 14 overvoltage overvoltage -9 13 -12 12 undervoltage -15 undervoltage 11 10 -50 -25 0 25 T 50 [OC] 75 100 125 150 -18 -50 -25 0 25 50 75 100 125 150 Figure 8. 3.3V/5V Dmon fault thresholds 0 -3 -6 Figure 11. ACsense and external voltage references 2.7 [V] VDMON [V] +5V overvoltage 2.6 +5V undervoltage -9 +3.3V overvoltage -12 2.5 +3.3V undervoltage -15 -18 -50 -25 0 25 50 75 100 125 150 T [OC] 2.4 2.3 -50 -25 0 25 50 75 100 125 150 T [OC] Figure 9. -12V bias current -20 Figure 12. Error amplifier A, B and C reference voltage 3 [V] -30 2.5 A 2 -40 1.5 1 B-C -50 -50 -25 0 25 50 75 100 125 150 0.5 -50 -25 0 25 50 T [ OC] 75 100 125 150 13/28 L6611 TYPICAL ELECTRICAL CHARACTERISTICS (continued) Figure 13. Error amplifiers (A, B, C) Gain and Phase 200 150 100 50 0 -50 -100 -150 -200 1e+00 1e+01 1e+02 1e+03 1e+04 1e+05 1e+06 1e+07 7e+07 gain phase 90 o mf 180 o 0o 14/28 L6611 APPLICATION INFORMATION INDEX 1 On board digital trimming and mode selection..................................................................................Page 16 2 Error amplifiers and reference voltages ..................................................................................................... 18 Main section: error amplifier A and Soft -Start E/A and reference voltage 3.3V section: error amplifier B Auxiliary section: error amplifier C 3 Normal operation timing diagram ............................................................................................................... 20 4 Undervoltage, overvoltage and relevant timings ........................................................................................ 21 5 AC sense (mains undervoltage warning) ................................................................................................... 22 6 Application example ................................................................................................................................... 23 7 Application ideas ........................................................................................................................................ 25 15/28 L6611 APPLICATION INFORMATION 1 ONBOARD DIGITAL TRIMMING AND MODE SELECTION By forcing the PROG input pin high, the chip enters programming mode: the multifunction pins PW_OK and PS_ON are then disconnected from their normal functions (output pins) and are connected to internal logic as DATA and CLOCK inputs respectively, allowing chip programming even when the device is assembled on the application board. Onboard chip programming allows: - selecting some working options; - reference voltage setpoints adjusting. It is also possible to verify the expected results before programming the chip definitively, in first instance, data can be loaded into a re-writeble volatile memory (a flip-flop array) where they are kept as long as the chip is supplied and can be changed as many times as one desires. A further operation is necessary to confirm the loaded data and permanently store them into a PROM (a poly-fuse array) inside the IC. Several steps compose the trimming/programming process: 1. PROG pin is forced high; 2. a clock signal is sent to the PS-ON/clock pin; 3. a byte with the following structure: MSB D3 D2 Data D1 D0 A3 A2 Address A1 A0 LSB is serially sent to the PW-OK/DATA pin and loaded into the IC's volatile memory bit by bit on the falling edges of the clock signal (see Fig. 14); "Address" is the identification code of the parameter that has to be trimmed and "Data" contains the tuning bits; 4. PROG pin is forced low (warning: Vdd must never fall below VddUVL0 during this process otherwise the contents of the volatile memory will be lost) and the result of the previous step is checked; 5. after any iterations of the steps 1-4 that might be necessary to achieve the desired value, force PROG pin high and send the following burn code MSB 0 0 0 0 1 1 1 1 LSB to permanently store the data in the PROM memory. Table 1 shows the list of the 6 programmable classes of functions, each one identified by a different code A0..A3, and the corresponding trimmable parameter(s); in table 2 it is possible to find the trim coding for the E/ A reference setpoints and in table 3 all the selections mode option coding are showed. The timing diagram of fig. 14 shows the details of data acquisition. Table 1. Programmable functions Address 0001 0010 0011 0100 0101 Parameter(s) Error amplifier A threshold Error amplifier B threshold Error amplifier C threshold AC sense threshold AC sense hysteresis Latch/Bounce mode selection Enable/Disable 12V UV/OV function 0110 Enable/Disable 5V UV/OV function 5V/3V3 Dmon selection Default value 2.50V 1.25V 1.25V 2.50V 50A Latch mode Enabled Enabled 5V selection D3 D3 D2 D1 don't care D3 D3 D3 D3 Tuning bits D2 D2 D2 D2 D2 D1 D1 D1 D1 D1 DO DO DO DO DO 16/28 L6611 Table 2. Trim Coding Parameter Address Tuning Bits D3 D2 D1 D0 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 E/A A threshold 2.5V typ. 0001 D3 D2 D1 D0 V [mV] +112 +96 +80 +64 +48 +32 +16 0 -16 -32 -48 -64 -80 -96 -112 -128 E/A B threshold 1.25V typ. 0010 D3 D2 D1 D0 V [mV] +56 +48 +40 +32 +24 +16 +8 0 -8 -16 -24 -32 -40 -48 -56 -64 E/A C threshold 1.25V typ. 0011 D3 D2 D1 D0 V [mV] +56 +48 +40 +32 +24 +16 +8 0 -8 -16 -24 -32 -40 -48 -56 -64 ACsns threshold 2.5V typ. 0010 D3 D2 D1 D0 V [mV] +112 +96 +80 +64 +48 +32 +16 0 -16 -32 -48 -64 -80 -96 -112 -128 +7.5 +5.0 +2.5 0 -2.5 -5.0 -7.5 -10 ACsns Hysteresys 50A typ. 0101 D2 D1 D0 I [A] Table 3. Mode coding Parameter Address Bit Value D3 0 1 Latch Bounce D3 Enabled Disabled Bounce or Latch Mode A3 A2 A1 A0 0101 Enable/Disable 12V UV/OV Enable/Disable 5V UV/OV A3 A2 A1 A0 0110 Tuning Bit D2 Enabled Disabled D1 5V 3.3V 5V/ 3.3V Dmon Selection Figure 14. Trimming/programming procedure: timing diagram MSB 0 PROG PS_ON/Clock PW_OK/Data 1 0 1 0 0 0 LSB 1 17/28 L6611 2 ERROR AMPLIFIERS AND REFERENCE VOLTAGES Three error amplifiers are implemented on the IC to achieve regulation of the output voltages: a brief description follows for each section. - Main section: error amplifier A and Soft-Start. The circuit is designed to directly control the Main primary PWM through an optocoupler, providing very good regulation and galvanic isolation from the primary side. Typical solutions require a shunt regulator, like the TL431, as a reference and feedback amplifier to sense the output voltage and generate a corresponding error voltage; this voltage is then converted in a current transferred to the primary side through the optocoupler. The feedback E/A amplifier is integrated in the IC: its non-inverting input is connected to an internally generated voltage reference, whose default value is typically 2.5V. It can however be trimmed to obtain a better precision (see "On board trimming and mode operating" section). Then, no TL431 is needed. The E/A inverting input (Ainv, pin#5) and the E/A output (Aout, pin#4) are externally available and the frequency compensation network (Zc) will be connected between them (see fig. 15). The high impedance (in the hundred k) internal divider from 12V and 5V UV/OV sense pins eliminates the need for an external one in most applications, allowing a further reduction in the number of external component. Under closed loop condition, the two upper branches, connected to 12V and 5V pins, supply equally the current flowing through R3= 80.6K (equal to 2.5V/R3). In order to avoid high current peaks in the primary circuit and output voltage overshoots at start-up, the IC provides an on-board 8ms soft-start, a quasi-monotonic ramp from 0V to 2.5V for the A error amplifier reference voltage,. In fact, if this reference gets the nominal value as soon as the power-up occurs, the A E/A will go out of regulation and tend to sink much more current, thus forcing PWM to work with the maximum duty-cycle. - E/A and references voltage Being the inverting input of E/A externally available, it is possible to change the "weight" of the two contributions or even eliminate one of them by connecting external resistors of much lower value (RL, RH1 and/or RH2 in fig. 15) that bypass the internal ones appropriately. For example using RL=2.4K, R H1=3.9K and RH2=24K, then the ratio between +5V and +12V output weight will be equal to 6:4. By simply making RH1 = RL (for example 2.4K) with no RH2, only the +5V output is kept under feedback because the contribution of +12V branch (through the internal 600K resistor) will be negligible. The pin #24 (12V) has to be connected to +12V output to guarantee the OV/UV monitoring. Figure 15. Main feedback section VDD to MAIN control RB +12V output +5V output 5V 168K Aout _ + 8ms SS 12V RH1 600K Ainv RH2 optional, to change feedback weight 80.6K GND RL L6611 +2.5V Zc - 3.3V section, error amplifier B. It is the error amplifier used to set the magamp core through an external circuitry (see a typical schematic in figure 16). The non-inverting input of the error amplifier is connected to a trimmable 1.25V internal voltage reference (see "On board trimming and mode operating" paragraph). The E/A inverting input is externally available (Binv, pin#2) and is connected to the output divider (RH and R L); the output pin (Bout, 18/28 L6611 pin#3) drives the external circuitry that biases the magamp core. Between these pins it is connected the compensation network (ZC). The maximum positive output voltage is clamped at about 3.5V to improve response time. The feedback control circuit determines the magamp "off" time, converting the voltage at the output of error amplifier into a current IR, which resets the magamp. If the output voltage exceeds its preset value, V(Bout) decreases; this causes a higher voltage across RC which, in turn, implies a larger voltage across R E and a larger reset current IR (VBE of Q1 is supposed constant). A larger IR causes the PWM waveform across D2 to get narrower. This pulls the output voltage back to the desired level and achieves regulation. It is possible to use this section to drive a pass transistor to obtain 3.3V with a linear regulator; in the "Application idea" section an example is showed to implement this solution. Figure 16. Magamp control feedback section +3.3V magamp D2 D1 Zc IR RE Q1 RC Bout RS L6611 _ + +1.25V Binv VD2 L C RH RL - Auxiliary section, error amplifier C. This section (fig. 17) provides the feedback signal for the auxiliary converter following the same operating principles as the Main section. The auxiliary output voltage (Vaux) is often defined as "Standby voltage" because the converter remains alive during standby condition (the Main converter is stopped) to supply the chip and all the ancillary circuits. Typical values for its output voltage are 5V or 3.3V. The inverting input (Cinv, pin#7) is connected to the output voltage through an external resistor divider whereas the non-inverting one is connected to a 1.25V trimmable internal voltage reference (see "On board trimming and mode operating" paragraph). The compensation network Zc(aux) is placed between E/A inverting input and output pins. When Dmon recognizes an undervoltage condition on the auxiliary output, an internal n-channel MOS (in open drain configuration) grounds E/A output pin; the high current flowing through the optocoupler is then transferred to the primary side causing a duty cycle as short as possible; this prevents a high energy transfer from primary to secondary under short circuit conditions, thus reducing the thermal stress on the power components. Figure 17. Auxiliary feedback section VAUX to AUX control RH RB Zc(aux) DMON _ Cout + OCP bounce GND +1.25V L6611 Cinv RL 19/28 L6611 3 NORMAL OPERATION TIMING DIAGRAM (FIG. 18) The time intervals t1-t5 are listed below - t1: UV/OC blanking of MFAULT. While Main outputs are ramping up, the UV comparators are blanked for this interval to prevent a false turn-off. No such blanking is applied to OV faults. - t2: PW-OK delay. This period starts when all monitored outputs and AC sense are above their respective UV levels and finishes at PW-OK going high. - t3: PS-ON debounce period. The voltage on PS-ON must be continuously present in a high or low state for a minimum period for that state to be recognized. - t4: Tdelay. The time from PS-ON being recognized as going high to MFAULT going high. This is to provide a power down warning. When PS-ON requests power off, PW-OK goes low immediately. - t5: UV blanking of DFAULT. During initial power up a period of UV blanking is applied to DFAULT as soon as Vdd to the chip is in the correct range. No such blanking is applied to OV faults. Figure 18. Normal Operation Timing Diagram (ON/OFF with PS-ON or the AC power switch). On AC Vdd Vdd-ok Off Vdd(on) Vdd(on) t5 UVBdfault ACsns Off ACsns_high ACsns_low PS-ON Mfault Main OPs On t3 t3 t2 t4 t2 POK UVBmfault t1 t1 20/28 L6611 4 UNDERVOLTAGE, OVERVOLTAGE, DETECTION AND RELEVANT TIMINGS The IC provides on-board undervoltage and overvoltage protection for 3V3, 5V, 12V Main input pins and Dmon auxiliary input pin. Overcurrent protection is available for 12V and 5V or 3.3V, digitally selectable. The internal fault logic is illustrated in figure 19. Figure 19. Simplified Fault logic Main_OV +/-12V_Main_UV +3V3 +5V_Main_UV ACsense + Debounce 6s Debounce 6s In Clock Out Reset In Clock Out Reset Reset Reset S Q Latch Mfault Debounce 500s In Clock Out Reset Vdd UVB 64ms In Clock Out Reset R Reset Vref Vdd Dmon_OV Debounce 6s In Clock Out Reset S Latch Q Dfault Reset Reset R Dmon_UV Vdd_OV Vdd_UVL Restart Mode Debounce 500s In Clock Out Reset Reset Vdd UVB 64ms In Clock Out Reset Cout D_UVB Reset S Latch Q Reset Delay 1s In Clock Out Reset Reset R Reset Delay 2.5ms In Clock Out Reset Vdd Reset Vdd Delay 250ms In Clock Out Reset S Latch Q PW-OK Vdd R PS-ON Debounce 75ms In Clock Out Reset ON - Main inputs overvoltage: whenever one of main outputs (3.3V, +5V, 12V) is detected as going overvoltage, MFAULT is latched high (which stops the Main PWM) and PW-OK goes low. Cycling the PSON switch or reducing Vdd below its undervoltage threshold releases the latch. A delay of 6s is implemented before MFAULT latching. The OV protection for the 12V and 5V outputs can be disabled (see "On board trimming and mode operating" section). - Main inputs undervoltage: when an undervoltage on main outputs is detected, MFAULT is latched high (the Main PWM stops) and PW-OK goes low. The latches are released, by default, cycling the PSON switch or reducing Vdd below its undervoltage threshold (latching mode); optionally, an attempt is made to restart the supply after of 1 second (bounce mode). The choice depends on the selected mode (see "On board trimming and mode operating" section). Debounce logic is implemented for 3.3V and 5V so that an undervoltage condition on these signals has to last 450s to be recognized as valid while 6s debounce logic is implemented for 12V and -12V input signal. When all main undervoltages are over and ACsns is OK (see the relevant section), PW_OK goes high after a delay of 250ms. - Dmon input overvoltage: whenever the Dmon input pin is detected as going overvoltage, both MFAULT and DFAULT are latched high. The latch is released by reducing Vdd below its undervoltage threshold. Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the overvoltage condition lasts more than 6s. To protect the load against overvoltage, typical solutions make use of a power crowbar (SCR) driven by 21/28 L6611 DFAULT; in the "Application ideas" section, another simple circuit is showed to guarantee the same protection without the SCR. - Dmon input undervoltage: when an undervoltage on Dmon is detected, MFAULT is put high, Cout is pulled low (an internal OCP_BOUNCE signal is generated, see fig. 19) and PW_OK falls down. This function is enabled 64ms after the UVLO signal falls down. Debounce logic is implemented so that MFAULT and OCP_BOUNCE signals are generated only if the undervoltage condition lasts more than 500s. The Dmon UV and OV protections can be set to work with thresholds set for 5V or 3.3V output voltage: the choice depends on the IC programming. Figure 20. Fault timing diagram Output Output Mfault Mfault POK POK Main output's overvoltage Main output's undervoltage Dmon(*) Dmon(*) Dfault current Cout Mfault Mfault POK POK Auxiliary output's overvoltage (*) Dmon is connected to the Auxiliary output Rail Auxiliary output's undervoltage 5 AC SENSE (MAINS UNDERVOLTAGE WARNING) The device monitors the primary bulk voltage and warns the system when the power is about to be lost pulling down the PW_OK output. The ACsns pin is typically connected to one of the windings of the main transformer (see fig. 21). Through a single-diode rectification filter, a voltage equal to VB = VBULK/N (where VBULK is the voltage across the bulk capacitor on primary side and N is the transformer turn ratio) is present at point B. A resistor (RF) could be useful to clamp voltage spikes present. The fault signal is generated by means of AC_GOOD, the output of an internal comparator; this comparator is internally referred to a trimmable 2.5V reference and indicates an AC fault if the voltage applied at its externally available (non-inverting) input is below the internal reference, as shown in fig. 21. This comparator is provided with current hysteresis instead of a more usual voltage hysteresis: an internal 50A current generator is ON if the voltage is below 2.5V and is turned off when the voltage applied at the non-inverting input exceeds 2.5V. This approach provides an additional degree of freedom: it is possible to set the ON threshold and the OFF 22/28 L6611 threshold separately by properly choosing the resistors of the external divider. The following relationships can be established for the ON (VB (ON)) and OFF (VB (OFF)) thresholds of the input voltage: VB ( O N ) - 2.5 2.5 --------------------------------- = ------- + 50 A R1 R2 which, solved for R1 and R2, yields: VB ( O N ) - VB ( O FF ) R 1 = -----------------------------------------------50 A 2.5 R 2 = R 1 -----------------------------------VB ( O FF ) - 2.5 R2 VB ( O FF ) -------------------- = 2.5 R1 + R 2 Both the ACsns threshold and the hysteresis current can be trimmed (see "On board trimming and mode operating" section). Figure 21. ACsns circuit and timing diagram L6611 RF +2.5V B _ + VB VB(on) R1 ACsns R2 IHYS=50A GND C1 AC_GOOD VB(off) AC_GOOD VACsns =50A*R1 PW_OK ON 6 APPLICATION EXAMPLE In applications like desktop PC's, server or web server, the system usually consists of two converters (Main and Auxiliary) that can be supplied directly from either the AC Mains or a PFC stage. The control and supervision at the secondary side is usually entrusted to a housekeeping circuit. The Auxiliary section supplies a stand-by voltage (5V typ.) through a flyback converter. The Main section, in forward configuration, presents 4 standard outputs (3.3V, +5V, 12V). At the secondary side, the housekeeping circuitry governed by the L6611 checks the outputs and sends control signals to the primary side through three optocouplers. It also generates power good information to the system while managing all timings during power-up and power-down sequences. In fig. 22 a detailed circuit for the secondary side is presented; it is possible to note the very low number of external components required. Simply connecting the power supply outputs to the L6611 relevant pins ensures the protection against over/undervoltage in the Main section. A crowbar on the auxiliary output is switched on through DFAULT in case of overvoltage. The L6611 is supplied by the Auxiliary output; the signals sent to the primary side are: - a "digital" ON/OFF signal through an optocoupler that drives the relevant pin of primary Main controller to switch the Main converter ON and OFF; - two analog signals that provide voltage feedback for both the Auxiliary and the Main section, driving the primary controller pins responsible for the duty cycle modulation. 23/28 L6611 Figure 22. Detailed Secondary Side +12V +5V COM -12V +3.3V 24/28 PRIMARY SIDE CONTROL & POWER MANAGEMENT L6611 M-FAULT Binv Bout Aout Ainv Cout Cinv DMON DFAULT Vdd 12V 5V 3V3 PROG GND -12 VREF PS-ON PW-OK ACsns +5Vaux L6611 7 APPLICATION IDEAS In fig. 23 a circuit is suggested to obtain the regulated +3.3V output with a linear configuration instead of the Magamp circuitry. In this case the output of the E/A modulates the gate-source voltage of a power MOS in series with the power stage. In fig. 24 a simple and cheap latch circuit is showed to manage an OV fault on the Auxiliary output in the same way of an OC (UV) fault, without having recourse to a (expensive) power crowbar. By tuning the value of RSET it is possible to set the voltage value that triggers the latch circuit; C DEL defines the turn-on delay. A diode connected between the collector of Q1 and Cout pulls down the output of the auxiliary E/A: this has the same effect of the OCP_bounce internal signal that guarantees the reduction of duty cycle. Figure 23. Controlling a Linear Regulator with the Error Amplifier B +5V +3.3V L C1 ZC +12V RB Bout L6611 _ Binv + +1.25V RL C2 RH Figure 24. Auxiliary OVP without Crowbar 100 DMON D1 BAT42 5K6 Q2 BC558 CDEL 5K6 VAUX RSET Cout L6611 Q1 BC548 25/28 L6611 DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.254 1.39 mm TYP. MAX. MIN. 0.010 1.65 0.45 0.25 25.4 8.5 2.54 22.86 7.1 3.93 3.3 1.34 0.055 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.065 0.018 0.010 1.000 0.335 0.100 0.900 0.280 0.155 0.130 DIP20 0.053 26/28 L6611 mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050 OUTLINE AND MECHANICAL DATA SO20 0 (min.)8 (max.) L h x 45 A B e K H D A1 C 20 11 E 1 0 1 SO20MEC 27/28 L6611 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 28/28 |
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